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? semiconductor components industries, llc, 2010 march, 2010 ? rev. 2 1 publication order number: cat4109/d cat4109 3-channel constant-current rgb led driver with individual pwm dimming description the cat4109 is a 3 ? channel constant ? current led driver, requiring no inductor. led channel currents up to 175 ma are programmed independently via separate external resistors. low output voltage operation of 0.4 v at 175 ma allows for more power efficient designs across wider supply voltage range. the three led pins are compatible with high voltage up to 25 v supporting applications with long strings of leds. three independent control inputs pwm1, pwm2, pwm3, control respectively led1, led2, led3 channels. the device also includes an output enable (oe) control pin to disable all three channels independently of the pwmx input states. thermal shutdown protection is incorporated in the device to disable the led outputs whenever the die temperature exceeds 150 c. the device is available in a 16 ? lead soic package. features ? 3 independent current sinks up to 175 ma rated 25 v ? led current set by external low power control resistors ? individual pwm control per channel ? low dropout current source (0.4 v at 175 ma) ? output enable input for dimming ? ?zero? current shutdown mode ? 3 v to 5.5 v logic supply ? thermal shutdown protection ? 16 ? lead soic package ? these devices are pb ? free, halogen free/bfr free and are rohs compliant application ? multi ? color led, architectural lighting ? led signs and displays ? lcd backlight http://onsemi.com soic ? 16 v suffix case 751bg pin connections marking diagram (top view) device package shipping ordering information cat4109v ? gt2 (note 1) soic ? 16 (pb ? free) 2,000/ tape & reel 1. lead finish nipdau l4a cat4109vb ymxxxx 1 pgnd gnd pwm3 pwm1 pwm2 vdd oe nc nc nc led1 led2 led3 rset3 rset2 rset1 l = assembly location 4 = lead finish ? nipdau a = product revision (fixed as ?a?) cat4109v = device code b = leave blank y = production year (last digit) m = production month (1 ? 9, a, b, c) xxxx = last four digits of assembly lot number
cat4109 http://onsemi.com 2 red green blue led3 led1 led2 vdd vin 5 v to 25 v vdd 3 v to 5.5 v c1 1 f oe pwm1 controller pwm2 pwm3 rset1 rset2 rset3 gnd pgnd cat4109 r1 r2 r3 figure 1. typical application circuit table 1. absolute maximum ratings parameter rating units vdd voltage 6 v input voltage range (oe, pwm1, pwm2, pwm3) ? 0.3 v to 6 v v led1, led2, led3 voltage 25 v dc output current on led1 to led3 200 ma storage temperature range ? 55 to +160 c junction temperature range ? 40 to +150 c lead soldering temperature (10 sec.) 300 c esd rating on all pins: human body model machine model 2000 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 2. recommended operating conditions parameter range units vdd 3.0 to 5.5 v voltage applied to led1 to led3, outputs off up to 25 v voltage applied to led1 to led3, outputs on up to 6 (note 2) v output current on led1 to led3 2 to 175 ma ambient temperature range ? 40 to +85 c 2. keeping ledx pin voltage below 6 v in operation is recommended to minimize thermal dissipation in the package.
cat4109 http://onsemi.com 3 table 3. electrical operating characteristics (min and max values are over recommended operating conditions unless specified otherwise. typical values are at v dd = 5.0 v, t amb = 25 c.) symbol name conditions min typ max units dc characteristics i dd1 supply current outputs off v led = 5 v, r set = 24.9 k 2 5 ma i dd2 supply current outputs off v led = 5 v, r set = 5.23 k 4 10 ma i dd3 supply current outputs on v led = 0.5 v, r set = 24.9 k 2 5 ma i dd4 supply current outputs on v led = 0.5 v, r set = 5.23 k 4 10 ma i shdn shutdown current v oe = 0 v 1 a i lkg led output leakage v led = 5 v, outputs off ? 1 1 a r oe oe pull ? down resistance 140 190 250 k v oe_ih v oe_il oe logic high level oe logic low level 1.3 0.4 v v pwm_ih v pwm_il pwmx logic high level pwmx logic low level 0.7 x v dd 0.3 x v dd v i il logic input leakage current (pwmx) v pwmx = v dd or gnd ? 5 0 5 a v rsetx rsetx regulated voltage 1.17 1.2 1.23 v t sd thermal shutdown 150 c t hys thermal hysteresis 20 c i led /i rset rset to led current gain ratio 100 ma led current 400 v uvlo undervoltage lockout (uvlo) threshold 1.8 v table 4. recommended timing (min and max values are over recommended operating conditions unless specified otherwise. typical values are at v dd = 5.0 v, t amb = 25 c.) symbol name conditions min typ max units t ps turn ? on time, oe rising to i led from shutdown i led = 100 ma 1.4 s t p1 turn ? on time, oe or pwmx rising to i led i led = 100 ma 600 ns t p2 turn ? off time, oe or pwmx falling to i led i led = 100 ma 300 ns t r led rise time i led = 100 ma 300 ns t f led fall time i led = 100 ma 300 ns t lo oe low time 1 s t hi oe high time 5 s t pwrdwn oe low time to shutdown delay 4 8 ms
cat4109 http://onsemi.com 4 output enable shutdown shutdown 0 ma shutdown 0 ma 0 ma shutdown 0 ma shutdown 0 ma led current vin quiescent current 50% 50% 90% 10% figure 2. cat4109 oe timing t hi t pwrdwn t lo t f t ps t p2 t p1 i led = (1.2 v/r set ) x 400 t r oe operation the output enable (oe) pin has two primary functions. when the oe input goes from high to low, all three led channels are turned off. if oe remains low for longer than t pwrdwn , the device enters shutdown mode drawing ?zero current? from the supply. the oe input can be used to adjust the contrast of the rgb led by applying an external pwm signal. the device has a very fast turn ? on time (from oe rising to led on) allowing ?instant on? when dimming leds. when applying pwm signals to the three pwmx inputs and using the oe pin for dimming, the oe pwm frequency should be much lower to preserve the color mixing. accurate linear dimming on oe is compatible with pwm frequencies from 100 hz to 5 khz for pwm duty cycle down to 1%. pwm frequencies up to 50 khz can be supported for duty cycles greater than 10%. when performing a combination of low frequencies and small duty cycles, the device may enter shutdown mode. this has no effect on the dimming accuracy, because the turn ? on time t ps is very short, in the range of 1 s. to ensure that pwm pulses are recognized, pulse width low time t lo should be longer than 1 s. the driver enters a ?zero current? shutdown mode after a 4 ms delay (typical) when oe is held low.
cat4109 http://onsemi.com 5 typical performance characteristics (v in = 5 v, v dd = 5 v, c1 = 1 f, t amb = 25 c unless otherwise specified.) figure 3. quiescent current vs. input voltage (i led = 0 ma) figure 4. quiescent current vs. rset current input voltage (v) rset current ( a) 5.5 5.0 4.5 4.0 3.5 3.0 0.4 0.6 0.8 1.0 1.2 400 300 200 100 0 0 2.0 4.0 6.0 8.0 figure 5. quiescent current vs. input voltage (i led = 175 ma) figure 6. led current vs. led pin voltage input voltage (v) led pin voltage (v) 5.5 5.0 4.5 4.0 3.5 3.0 4.0 4.5 5.0 5.5 6.0 1.0 0.8 0.6 0.4 0.2 0 0 40 80 120 160 200 figure 7. led current change vs. input voltage figure 8. led current change vs. temperature input voltage (v) temperature ( c) 5.5 5.0 4.5 4.0 3.5 3.0 0 40 80 120 160 200 120 80 40 0 ? 40 0 40 80 120 160 200 quiescent current (ma) quiescent current (ma) quiescent current (ma) led current (ma) led current (ma) led current (ma) no load full load
cat4109 http://onsemi.com 6 typical performance characteristics (v in = 5 v, v dd = 5 v, c1 = 1 f, t amb = 25 c unless otherwise specified.) figure 9. rset pin voltage vs. input voltage figure 10. rset pin voltage vs. temperature input voltage (v) temperature ( c) 5.5 5.0 4.5 4.0 3.5 3.0 1.10 1.15 1.20 1.25 1.30 120 80 40 0 ? 40 1.10 1.15 1.20 1.25 1.30 figure 11. led current vs. rset resistor figure 12. oe transient response at 1 khz rset (k ) 60 45 30 15 0 0 40 80 120 160 200 rset voltage (v) rset voltage (v) led current (ma) figure 13. pwmx transient response
cat4109 http://onsemi.com 7 table 5. pin descriptions name pin number function pgnd 1 power ground. gnd 2 ground reference. pwm3 3 pwm control input for led3 pwm2 4 pwm control input for led2 pwm1 5 pwm control input for led1 rset3 6 led current set pin for led3 rset2 7 led current set pin for led2 rset1 8 led current set pin for led1 led3 9 led channel 3 cathode terminal led2 10 led channel 2 cathode terminal led1 11 led channel 1 cathode terminal nc 12 not connected inside package nc 13 not connected inside package nc 14 not connected inside package oe 15 output enable input pin vdd 16 device supply pin pin function pgnd is the power ground reference pin for the device. this pin must be connected to the gnd pin and to the ground plane on the pcb. gnd is the ground reference pin for the entire device. this pin must be connected to the ground plane on the pcb. pwm1 to pwm3 are the control inputs respectively for led1, led2 and led3 channels. when pwmx are low, the associated led channels are turned off. when pwmx are high, the corresponding channels are turned on, assuming the oe input is also high. pwmx pins can not be left open and must be set either to logic high or low. rset1 to rset3 are the led current set inputs. the current pulled out of these pins will be mirrored in the corresponding led channel with a gain of 400. led1 to led3 are the led current sink inputs. these pins are connected to the bottom cathodes of the led strings. the current sinks bias the leds with a current equal to 400 times the corresponding rsetx pin current. for the led sink to operate correctly the voltage on the led pin must be above 0.4 v. each led channel can withstand voltages up to 25 v. oe is the output enable input. when high, all led channels are enabled according to the state of their corresponding pwmx control inputs. when low, all led channels are turned off. this pin can be used to turn all the leds off independently of the state of the pwmx inputs. if the oe stays low for a duration longer than t pwrdwn , the device enters shutdown mode. vdd is the positive supply pin voltage for the entire device. a small 1 f bypass ceramic capacitor is recommended between vdd pin and ground near the device.
cat4109 http://onsemi.com 8 block diagram current setting 1.2 v ref + rset1 current setting rset2 current setting rset3 oe vdd led1 led2 led3 pwm3 current sinks pwm2 pwm1 gnd pgnd figure 14. cat4109 functional block diagram basic operation the cat4109 uses 3 independent current sinks to accurately regulate the current in each led channel to 400 times the current sink from the corresponding rset pin. each of the resistors tied to the rset1, rset2, rset3 pins set the current respectively in the led1, led2, and led3 channels. table 6 shows standard resistor values for rset and the corresponding led current. table 6. rset resistor settings led current [ma] rset [k ] 20 24.9 60 8.45 100 5.23 175 3.01 tight current regulation for all channels is possible over a wide range of input and led voltages due to independent current sensing circuitry on each channel. the led channels have a low dropout of 0.4 v or less for all current ranges and supply voltages. this helps improve heat dissipation and efficiency. upon power ? up, an under ? voltage lockout circuit sets all outputs to of f. once the vdd supply voltage is greater than the under ? voltage lockout threshold, the device channel can be turned on. the on/off state of each channel led1, led2 and led3 is independently controlled respectively by pwm1, pwm2, pwm3. when a pwmx is high, the associated ledx channel is turned on.
cat4109 http://onsemi.com 9 application information power dissipation the power dissipation (p d ) of the cat4109 can be calculated as follows: p d v dd i dd v ledn i ledn where v ledn is the voltage at the led pin, and i ledn is the associated led current. combinations of high v led voltage or high ambient temperature can cause the ca t4109 to enter thermal shutdown. in applications where v ledn is high, a resistor can be inserted in series with the led string to lower p d . thermal dissipation of the junction heat consists primarily of two paths in series. the first path is the junction to the case ( jc ) thermal resistance which is defined by the package style, and the second path is the case to ambient ( ca ) thermal resistance, which is dependent on board layout. the overall junction to ambient ( ja ) thermal resistance is equal to: ja jc ca for a given package style and board layout, the operating junction temperature t j is a function of the power dissipation p d , and the ambient temperature, resulting in the following equation: t j t amb p d ( jc ca ) t amb p d ja when mounted on a double ? sided printed circuit board with two square inches of copper allocated for ?heat spreading?, the resulting ja is about 74 c/w. for example, at 60 c ambient temperature, the maximum power dissipation is calculated as follow: p dmax (t jmax t amb ) ja (150 60) 74 1.2 w recommended layout bypass capacitor c1 should be placed as close to the ic as possible. rset resistors should be directly connected to the gnd pin of the device. for better thermal dissipation, multiple via can be used to connect the gnd pad to a large ground plane. it is also recommended to use large pads and traces on the pcb wherever possible to spread out the heat. the leds for this layout are driven from a separate supply (vled+), but they can also be driven from the same supply connected to vdd. figure 15. recommended layout
cat4109 http://onsemi.com 10 package dimensions soic ? 16, 150 mils case 751bg ? 01 issue o top view pin#1 identification e d a e b a1 l h c e1 side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 9.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 10.00 6.20 4.00 l 0.40 1.27 1.35 9.90 6.00 3.90
cat4109 http://onsemi.com 11 example of ordering information (note 5) prefix device # suffix company id cat 4109 product number 4109 t2 t: tape & reel 2: 2,000 / reel tape & reel (note 7) v package v: soic ? g g: nipdau blank: matte ? tin lead finish (optional) 3. all packages are rohs ? compliant (lead ? free, halogen ? free). 4. the standard plated finish is nipdau. 5. the device used in the above example is a cat4109v ? gt2 (soic, nipdau, tape & reel, 2,000/reel). 6. for additional temperature options, please contact your nearest on semiconductor sales office. 7. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cat4109/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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